1. Field of the Invention
The present invention generally relates to a time-slot interchanger (TSI), and more particularly, to a time-slot interchanger which performs circuit cross connecting in a synchronous multiplexer used in a digital synchronous network.
2. Description of the Prior Art
In a digital synchronous network, by interchanging time slots in a digital multiplex signal, it becomes possible to perform circuit cross connecting in a time scale, instead of space cross connecting in a distribution frame which has been performed in a conventional analog network. To perform such circuit cross connecting, a synchronous multiplexer is in practical use. A circuit-cross-connecting function in the synchronous multiplexer is performed by a time-slot interchanger which interchanges time-and-space time slot positions in a data sequence. If the time-slot interchanger is constructed such that an order of interchanged time slots is controllable by an external signal, a controllable time switch may be realized.
FIG. 1 shows an example of a network using such a synchronous multiplexer. In FIG. 1, 4 add-drop multiplexers (ADM) are connected in a ring form through optical fiber cables. Between two of the ADMs, a multiplexed optical signal is transmitted through the optical fiber cable. Each of the ADMs is connected to a multiplexer (not shown).
FIG. 2 shows an example of a digital hierarchy of a multiplexed signal in the network shown in FIG. 1. The digital hierarchy shown in FIG. 2 comprises a first-order group to a sixth-order group. The ADMs shown in FIG. 1 transmit a fourth-order group signal STM-1 or a fifth-order group signal STM-4 to each other through the optical fiber cables. And the multiplexers (not shown) connected to the ADMs have a function of processing a third-order group signal shown in FIG. 2. In FIG. 2, C-n indicates a container, VC-n indicates a virtual container, TU-n indicates a tributary container, AU-n indicates an administrative unit, and STM-n indicates a synchronous transport module. Such a digital hierarchy is described in detail in other articles, for example, CCITT G707, G708, G709, and BT SPEC RC8876C.
FIG. 3 shows a configuration of the ADM shown in FIG. 1. In FIG. 3, each of the ADMs transmits the fifth-order signal STM-4 through the optical fiber cables (channel #1 and channel #2). In the ADM, for each channel #1, #2, an optic-to-electronic converter OR, a multiplexer MUX, and a demultiplexer DMUX are installed.
The multiplexer MUX multiplexes 4 fourth-order group signals STM-1, and produces the fifth-order group signal STM-4. The demultiplexer DMUX demultiplexes the fifth-order group signal STM-4 and produces the 4 fourth-order group signals STM-1. The multiplexer MUX and demultiplexer DMUX are connected to two multiplex/demultiplex equipment MUX/DMUX as shown in FIG. 3.
The demultiplexed signals STM-1 are supplied to ports DROP of one MUX/DMUX, and the signals STM-1 to be multiplexed are produced from port ADD of the other MUX/DMUX. And the one MUX/DMUX receives STM-1 signals from a lower-level multiplexer (not shown), and the other MUX/DMUX produces STM-1 signals to the lower-level multiplexer (not shown).
Further, between the two multiplex/demultiplex equipment MUX/DMUX, a time-slot interchanger TSI performing the circuit cross connecting is connected as shown in FIG. 3. As mentioned above, the time-slot interchanger TSI can interchange the time-slot positions in the data sequence in both the time scale and space scale.
FIG. 4 shows an illustration representing a concept of the time-slot interchanger TSI. Input data sequences 1C, 1B, 1A, and 2C, 2B, 2A are converted to parallel data in DMUXs. And in the time-slot interchanger TSI, time slots of the parallel data are interchanged in the time scale and space scale, and are output as serial data from MUXs.
FIG. 5 shows an illustration representing data processing of the time-slot interchanger TSI. Interchange of the time-slot position in the data sequence in the time scale and space scale are performed by a time-space-time (TST) function which includes 2 time switches of a front time switch (FTSW) and a rear time switch (RTSW), and 1 space switch (SSW). These three switches operate at the same timing.
Three data sequences A, B, and C, whose times-lot positions are respectively interchanged in the front time switch FTSW, are output to the space switch SSW. In the front time switch FTSW, a blank region is added to each of the data sequences. Thus, an amount of data doubles. Therefore, each switch needs to operate at twice a bit rate of the data sequence.
In the front switch FTSW which is constructed with memories, the input data sequence is written into the memory according to a sequential writing address supplied from a program counter (PG), and then, according to a random reading out address supplied from an address control memory ACM, sequentially written input data is read out at random.
The space switch SSW interchanges in the space scale the time-slot positions of the received data, and produces it to the rear time switch RTSW. The space switch SSW is also constructed with memories. This space interchange of the time-slot positions is controlled by producing a selection signal SEL (address) to be given to this switch from the switch control memory ACM.
The rear time switch RTSW is also constructed with memories. In the rear time switch RTSW, the input data from the space switch SSW is written into the memory according to the sequential writing address, and written data is read out at random according to a random reading address supplied from the switch control memory ACM.
In this way, the time-slot positions in the input data are interchanged in the time scale and space scale, as shown in FIG. 5.
FIGS. 6A to 6E shows illustrations for explaining the blank region shown in FIG. 5. The blank region is used for preventing a blocking from generating in the operation of the space switch SSW.
Now, two input data sequences, an input 1 and an input 2, are represented in FIG. 6A. The input 1 includes data .alpha., .tau., .epsilon., .sigma., .pi., and the input 2 includes data a, b, c, d, e. The input 1 and the input 2 are sequentially written into memories in front time switch FTSW. Output data sequences of the TST function are represented by a request 1 and a request 2, as shown in FIG. 6B. In this case, the blocking can be prevented by using the blank regions as shown in FIGS. 6C and 6D.
FIG. 6C shows operations of the front time switch FTSW (which are represented as a process 11 and a process 12). In an example shown in FIG. 6C, the blocking between the data .tau. and the data .epsilon., and the blocking between the data c and the data b are prevented. In the process 11, requested slots for the data .tau. and the data .epsilon. are set at the same time, but it is not difficult to read out both the data .tau. and the data .epsilon. from the memory in the FTSW at the same time. The above also covers the process 12 for the data c and the data b. Therefore, one of the data .tau. and the data .epsilon. and one of the data c and the data b need to be moved to the blank region. In the example shown in FIG. 6C, the data .epsilon. and the data b are moved to the blank region. And in the same example, the data .sigma. and the data d, which are output to another data sequence, are also moved to the blank region. In the drawing, a slot in which a designation of data is not written is meant to have the same data as that of a previous slot.
Then, as shown in FIG. 6D, in processes of the space switch (a process 21 and a process 22), an interchange of the slots including the blank region is performed in the space scale. In an example shown in FIG. 6D, the data d and the data .sigma. are interchanged, the data b is moved to an upper-side channel, and the data .epsilon. is moved to a lower-side channel.
Finally, as shown in FIG. 6E, in processes of the rear time switch RTSW (a process 31 and a process 32), unnecessary data corresponding to an amount of blank region is removed.
In this way, by adding the blank region, which has the same amount of data as that of the input data sequence, to the input data sequence, and processing the data at twice the bit rate of the input data sequence in each switch, the blocking may be prevented.
FIG. 7 shows a frame format of the signal STM-1 processed by the time-slot interchanger TSI shown in FIG. 3. The input data sequence (STM-1) constructs one frame with 270 bytes.times.9 ROW. This one frame comprises an overhead region (OHB: 9 bytes.times.9 ROW), and a data (payload) region (261 bytes.times.9 ROW). To such a single frame of the STM-1, a blank region of 270 bytes.times.9 ROW is added.
FIGS. 8A to 8C show illustrations for explaining in further detail the operation of the TST function in the conventional time-slot interchanger TSI. FIG. 8A shows an operation of the front time switch FTSW, FIG. 8B shows an operation of the space switch SSW, and FIG. 8C shows an operation of the rear time switch RTSW.
In FIG. 8A, the input data sequence is sequentially written into the front time switch FTSW (memory) in order of addresses 1, 2, 3, and is read out at random according to the addresses supplied from the switch control memory ACM. In this reading operation, to prevent the above-mentioned blocking, a blank region is added to the input data. In an example shown in FIG. 8A, the blank region comprising the data A, B, C is added to the end of the data sequence C, B, A.
The output data read out from the front time switch FTSW then is transmitted to the space switch SSW, as shown in FIG. 8B. In an example shown in FIG. 8B, the space switch SSW can receive the output data from three front time switches FTSWs. The operation of the space switch SSW is controlled by the addresses stored in the switch control memory ACM. For example, for an output channel #1 of the space switch SSW, the switch control memory ACM stores addresses 3, 1, 3 for the output data and also stores addresses 2, 3, 1 for the blank region. According to the addresses, to the channel #1, the output data of M, B, 0 and the blank-region data J, Q, F are produced. The same operation is performed in other channels.
Next, the output data of the space switch SSW shown in FIG. 8B is supplied to the rear time switch RTSW, as shown in FIG. 8C. The output data from the time switch SSW is sequentially written into the rear time switch RTSW (memory), and the data is produced according to the addresses supplied from the switch control memory ACM. In an example shown in FIG. 8C, the data sequence C, B, A, A, B, C is sequentially written into the rear time switch RTSW, and are interchanged according to the random addresses supplied from the ACM. And then, only the data C, B, A is read out from the rear time switch RTSW.
FIG. 9 shows a block diagram of the conventional time-slot interchanger TSI for realizing the data processing show in FIG. 8. This time-slot interchanger TSI has n-systems (n channels: n is an integer). Each channel has the front time switch FTSW and the rear time switch RTSW which are constructed with the memories, and one space switch SSW which is commonly used by the all channels.
Further, the switch control memory ACM is equipped with each switch. The switch control memories ACMs connected to the front time switch FTSW and the space switch SSW are controlled by an ACM-access-selection control unit ASLC. And the switch control memory connected to the rear time switch RTSW is controlled by an access control unit ACU. The access control unit ACU also controls the ACM-access-selection control unit ASLC.
The time-slot interchanger TSI mentioned above is controlled by a microprocessor unit MPU. The microprocessor unit comprises an address-control division unit ACD and a channel/column converter CCC. The front time switch, the rear time switch, and the space switch SSW are operative at the same external timing signal which is supplied to each switch control memory.
The MPU receives information set by a user. The information includes a length of each data (signal), and connection information of each channel. On the contrary, information requested by each switch is connection information of a byte unit. The channel/column converter CCC of the MPU has a function of converting a channel number input by the user to a byte number. The address-control division unit ACD determines how to connect the switches of the TST such that the connection information of each byte doesn't block each other, and produces determined connection information to the access control unit ACU. Each switch control memory ACM stores respective switch connection information which has been determined in the ACD.
Now, an operation of the time-slot interchanger TSI will be described. First, the information set by the user is converted to the connection information indicated in the byte unit by the channel/column converter CCC and the address-control division unit ACD, and the converted connection information is stored in the switch control memory ACM of each switch. This stored connection information is used for the reading address of the front time switch FTSW and the rear time switch RTSW.
As mentioned before, in each time switch, the input data is sequentially written into the time switch, and is temporarily stored, and then, is read out according to the connection information (address) from the switch control memory ACM. In this way, the slot interchange in the time scale is performed. In this interchange, to prevent the blocking, the blank region is added to the input data to produce twice the mount of the data in the front time switch FTSW, and the blank region is removed to produce only the required data having half the data input to the rear time switch RTSW. The time switch SSW interchanges the slots in the space scale. Therefore, there is no need for the switch to store the input data, and the data selection is performed according to the data supplied from the switch control memory ACM.
However, the above conventional techniques have the following problems:
(1) Recently, LSI technology is developing remarkably, and many efforts are directed to a miniaturization of a device by integrating separate functions into one LSI circuit. However, there still are restrictions of an operating speed, a circuit size, etc., and these restrictions are obstacles to realizing functions in a circuit design. PA1 (2) When the bit rate of the data is high, a problem that it is difficult to construct an interface circuit appears in addition to the high power consumption. A description of this problem will be given as follows by referring to FIGS. 10A and 10B. FIGS. 10A and 10B show illustrations for explaining the problem in the conventional device. PA1 (3) As shown in FIG. 9, each switch is operative at a single timing signal supplied from outside of the time-slot interchanger TSI. However, when a new time-slot interchanger TSI is designed for a conventional network, it is difficult to design the TSI such that a timing of the new TSI coincides with a timing of the conventional TSI. There is thus a problem that the conventional time-slot interchanger TSI shown in FIG. 9 has a disadvantages of a lack of application flexibility.
In further detail, to prevent the above-mentioned blocking, in the time-slot interchanger TSI, the blank region is added, and the data needs to be processed at twice the bit rate of the input data. For example, in FIG. 9, on the assumption that the bit rate of each input data is 19 Mbps, the data, to which the blank region is added, needs to be processed at a 38-Mbps operating speed. Each switch handling this data is usually constructed with CMOS circuits which may be extended to a large-scale gate. Therefore, there is a problem that a large power consumption is necessary for processing the data at 38 Mbps. Namely, the higher the bit rate of the data to be processed, the larger the power consumption. Therefore, it is not desired to process the 19-Mbps data at 38 Mbps from a standpoint of the power consumption.
FIG. 10A shows one case that an LSI2 produces data to an LSI1 in response to a clock signal CK from the LSI1. FIG. 10B shows time charts of signals at points [1] to [4] shown in FIG. 10A. In this case, the clock signal CK produced from the LSI1 is delayed in a transmission line to the LSI2, and as shown in the time chart [2] of FIG. 10B, the LSI2 receives a delayed clock signal. In synchronization with the delayed clock signal CK, a flip-flop FF in the LSI2 produces the data to the LSI1 at a timing (shaded part) shown in time chart [3]of FIG. 10B. The data produced from the LSI2 is also delayed in the transmission line to the LSI1. If the data is delayed by more than one period of the clock signal CK from a first rising edge thereof as shown in a time chart [4](shaded part ) of FIG. 10B, a flip-flop FF in the LSI1 cannot receive the delayed data at a second rising edge of the clock signal CK. In this way, when there is a large delay, a synchronous operation may not be performed. Further, for a higher clock speed, the above problem becomes remarkable.
Such a problem may occur at interfaces between the front time switch FTSW and the space switch, and between the space switch and the rear time switch. Therefore, to ensure data transmissions between them, it is not desired that the bit rate of the data be high.